TSMC Roadmap Lays Out Advanced CoWoS Packaging Systems, All set For Future-Gen Chiplet Architectures & HBM3 Memory

TSMC has laid out its innovative packaging engineering roadmap and showcased its future-gen CoWoS alternatives which are all set for next-gen chiplet architectures and memory options.

TSMC Lays Out Its Highly developed CoWoS Packaging Engineering Roadmap, 2023 Style and design Completely ready For Chiplet & HBM3 Architectures

The Taiwanese-based mostly semiconductor big has attained immediate development in deploying advanced chip packaging technologies in the market. Within a 10 years, the corporation has introduced five diverse generations of CoWoS (Chip-on-Wafer-on-Substrate) deals that are at this time deployed or staying deployed in shopper and server room.

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The corporation expects to release its Gen 5 CoWoS packaging alternative afterwards this year which will push the transistor count by 20x in excess of the 3rd Gen packaging alternative. The new package deal will arrive with an interposer place improve of 3 moments, 8 HBM2e stacks for up to 128 GB capacities, a brand new TSV solution, Thick CU interconnect, and a new TIM (Lid bundle). The most notable resolution that will make use of the Gen 5 packaging technological know-how from TSMC is particularly AMD’s MI200 ‘Aldebaran’ GPU.

The AMD Aldebaran GPU will be the initial MCM GPU fabricated and manufactured about at TSMC. The GPU will be powered by AMD’s CDNA 2 architecture and is predicted to rock some insane specs these as in excess of 16,000 cores and 128 GB of HBM2E memory. NVIDIA’s Hopper GPU would also be generating use of an MCM chiplet architecture and is expected to be made at TSMC. This GPU is anticipated to launch in 2022 so we can hope NVIDIA to leverage from the Gen 5 solution also.

By Gen 6, TSMC will have a much larger reticle space to combine extra chiplets and extra DRAM packages. The package structure has not but been finalized by TSMC expects to household up to 8 HBM3 DRAM and two compute chiplet dies on the similar package. TSMC is also heading to offer the latest SOC thermal resolution in the form of Metal Tim which is expected to decrease the bundle thermal resistance to .15x about Gel TIM utilised in 1st Gen. This is nevertheless far off and will be made for items that will be made on the N3 procedure node so we are searching at possibly CDNA 3 (MI300) or Ampere Up coming Subsequent.